[luau] Interesting question I found...

[Brandon Jasper]

The easiest way to do this is probably using Vmware ESX server and simply
use two virtual machines with the processor assigned to each.  The problem
is the ESX server is EXPENSIVE... The type where they don't list a price,
just give you a contact number.  I use the GSX server on some of my systems
though you'll have the overhead of the host OS with GSX, ESX is an operating
system optimized to run VMs... ESX is nice though, saw it running 40 virtual
machines on a mainframe system.

On 12/4/02 9:57 AM, "Charles Lockhart" <lockhart at jeans.ifa.hawaii.edu>
wrote:

> Sorry, I read this off of a different list.  Nobody seemed to be
> replying there, so I'm assuming they don't know.  Has anybody here know
> if this kind of thing is possible?  It sounds interesting, though not
> sure what the application would be.
> 
> *** begin excerpt from other email ***
> Sorry for beeing a little off topic, but this list appears to have
> many people that knows low level x86 programming (and PPC )
> very well.
> 
> We are looking at using a new motherboard or embedded board with dual
> PIII, P4 or Xeon processors. Theese boards have relatively modern
> chipsets that we have not much practical experience with. I have seen
> some postings about multiprocessor issues on this list.
> 
> My questions are :
> 
> We want to boot two separate stripped kernels so that one kernel runs on
> the first cpu and the other kernel runs on the other cpu (on the same
> board). No load sharing. Two separate schedulers. We only need access to
> two Gigabit Ethernet controllers(one for each cpu), common system
> memory, interrupt subsystem. No disk access, vga access, printer port
> access etc. is neccessary after the system has booted and the kernels
> are running.
> 
> Can somebody on this list assist me in telling what approach we have to
> follow to set up a standard dual processor motherboard so that the
> kernels can live "two separate lives" ? What changes must be done to
> lilo and to the kernel code so that there will be no register or memory
> conflicts?
> 
> How do we program the interrupt controller to direct interrupts to the
> correct CPU ? Are there any standard hardware API or standarized
> register sets to do this on the x86 platforms ?
> 
> Any input, contact persons, urls will be appreciated. Off list if
> appropriate.
> *** end excerpt from other email ***
> 
> _______________________________________________
> LUAU mailing list
> LUAU at videl.ics.hawaii.edu
> http://videl.ics.hawaii.edu/mailman/listinfo/luau